The invention relates to the field of semiconductor transistors utilizing a voltage applied to a gate contact to control current in a conductive channel. The device disclosed herein is particularly useful in the art of power transistors that operate in a wide range of temperatures. Transistors formed by the new method include a regrown P type epitaxial layer for the channel layer and thus exhibit better control at room temperature or even elevated temperatures.
Numerous efforts have been underway to develop silicon carbide MOSFETs using conventional DMOS (double diffused metal-oxide-semiconductor) structures with an N type regrown channel that improves channel mobility. The presence of the N type regrown channel causes inherent fluctuations in device performance because the threshold voltage shifts with operating conditions. Research shows that the varying threshold voltage results, at least in part, from scattered carriers distributed through the device during manufacturing steps, such as during channel layer regrowth, N type ion implantation, dopant activation, etc. In general, the N type regrown layer reduces the threshold voltage by about 1 volt as compared to standard transistors with no regrown channel layer. This change in threshold voltage leads to undesirable variations in conduction at both room temperature and elevated temperatures.
The innovative features of this invention are useful in several different semiconductor devices and are particularly effective in MOSFET designs. Commonly assigned U.S. Pat. No. 6,956,238 (Ryu 2005) sets forth a significant list of literature describing the history, structure, and performance characteristics of power MOSFETS. The Ryu '238 patent is incorporated by reference as if fully set forth herein. Generally, power MOSFETs utilize a gate contact to control conductivity in the semiconductor channel of the device. When the voltage on the gate is sufficiently high, the transistor will conduct large currents from source to drain so long as the appropriate inversion layer allows carriers from the source to cross into the drift region of the device.
Numerous efforts have been taken to develop SiC MOSFETs using conventional techniques, such as double diffusion. FIG. 1 shows an example. These appropriately named DMOSFETs (double diffused metal oxide semiconductor field effect transistors) include P type wells (12, 14) surrounding an N type source (16, 17) (or the opposite conductivity types depending on the type of device). For current to flow from source (16, 17) to drain (20) across a drift region (22), the traditional DMOSFETs (10) require a sufficient voltage on the gate contact (24) atop an oxide layer (26) to invert a channel region (28) in the P type well (12, 14) so that N type carriers from the source (16, 17) can traverse the wells (12, 14), cross the conductive drift region (22), and form a large current on the drain contact (20). See Prior Art FIG. 1.
As set forth in the Ryu '238 patent of the prior art, the p-wells of a DMOSFET are semiconductor regions implanted with aluminum or boron, and the source region is implanted with nitrogen or phosphorus. The implants are activated at temperatures between 1400° C. to 1700° C. The contacts to N+ layers are annealed layers of nickel (Ni) while the contacts to the P+ regions of the device would be nickel (Ni), titanium (Ti), or an alloy of titanium and aluminum (Ti/Al). A dielectric layer, such as silicon nitride or silicon dioxide, separates the gate contact from the semiconductor layer of the transistor. See U.S. Pat. No. 6,956,238 (Ryu, 2005) (Col. 2, Lines 44-55). Ryu notes (col. 2, lines 58-65) that one problem with DMOSFETs is poor mobility in the inversion layer, leading to very high on-resistance.
Ryu '238 previously alleviated this high on-resistance to a certain extent by forming a thin layer of silicon carbide over the well regions surrounding the source. This thin layer (26) is doped to N type conductivity with nitrogen or phosphorus and extends from the source region to the drift region. The thin semiconductor layer (26) provides a shorting channel for carriers from the source to traverse the well region, thereby enhancing conduction from source to drain. See Ryu '238 (col. 11, lines 33-38). In a different embodiment, Ryu utilizes a regrown epitaxial layer that is grown over the P type wells and extends across the drift region. See Ryu '238 (col. 12, lines 8-36). In this embodiment of Ryu's device, the regrown silicon carbide layer is undoped.
Ryu's silicon carbide regrown layer has a thickness from about 0.05 microns to about 1 micron, but a thinner layer of between about 1000 and 5000 angstroms is preferred. According to Ryu, the thin, N type shorting channels and regrown layers self deplete the channel at zero bias to prevent unwanted conduction in the off state. These layers also provide a low resistance route for source carriers to aid the inversion layer in providing conduction to the drain. Furthermore, the regrown layer reduces the surface roughness created by implant activation annealing. In this regard, the conductive channel is positioned in the epitaxial layer for better conductivity. See Ryu '238, col. 12, lines 30-35.
Ryu has achieved considerable advancement in controlling the zero bias state and preventing conductivity at that point while also providing a low on-resistance under forward biasing. Still, however, the presence of the N type regrown channel layer (26) causes fluctuation in the threshold voltage that turns on the device, partly because temperature variations affect channel depletion in the shorting channels and regrown layer. Interface states and electron scattering, natural results of Ryu's ion implantation and activation, further complicate the unpredictable threshold voltage in devices with Ryu's regrown layer. In fact, an N type regrown layer may reduce threshold voltage by as much as 1 V as compared to devices with no regrown layer. Accordingly, devices with an N type regrown layer may exhibit unwanted forward conduction at room temperature or other operating temperatures, even at zero gate bias.
Attempts to control threshold voltage, even in devices used at various operating temperatures, have previously manipulated the structural features of the conductive channel. For instance, U.S. Pat. No. 5,905,284 (Fuji, 1999) discusses the fact that as gate oxide films between the gate and the transistor body become increasingly thinner with device miniaturization, the gate impurities diffuse into the channel, causing unwanted conduction at zero gate bias. (Fuji, col. 2, lines 17-22). Fuji notes that one remedy to this problem may be found in forming the gate oxide films and gate contacts discretely, which, of course leads to higher manufacturing costs. Fuji then suggests a method of forming the diffusively doped regions in the transistor in defined layers with varying annealing temperatures and different angles of dopant implantation. (col. 4, lines 28-40; col. 13, lines 1-15).
In a different technique for ensuring the integrity of a device threshold voltage at operating temperatures, Han et al. show that the doping profile of the source is another way to manage conductivity in the channel. See EP 0744769 A2 (col. 10, lines 3-29). In Han's FIG. 5, as the phosphorus concentration in the channel decreases, the latch current density steadily increases, but the latch does not occur when the phosphorus doping is less than 5×1018 cm−3. All the while, forward current density decreases only slightly, further adding to Han's positive result. For general purposes, Han shows that as the phosphorus concentration decreases along the surface of the source, the size of the source is reduced vertically in Han's FIG. 1, so the length of the channel is increased. The P+ polarity in the channel is also increased, thereby maintaining a higher than expected threshold voltage. See Han '769 (col. 10, lines 25-30).
Even with Ryu's advances in increasing channel efficiency with regrown N type layers and other efforts in this area, a need still exists in the art of power electronics for a transistor with high conductivity in the channel without the corresponding deterioration in threshold voltage. Other attempts to manage the threshold voltage characteristics of power transistors require manipulating the source to an extent that maximum conductivity cannot be achieved. Accordingly, there exists a persistent need in the art for a power transistor with low on resistance, high channel conductivity, and a reliable threshold voltage even at a wide range of operating temperatures.